Memory suitable for operation at low power supply voltages and s

Details Memory suitable for operation at low power supply voltages and s Memory suitable for operation at low power supply voltages and s

1996-08-23

1998-03-17

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518533, 36518906, 36518907, 36518909, G11C 1606, G11C 1604

Patent

active

057294933

ABSTRACT:
A memory (400) includes a sense amplifier (500) formed with current-to-voltage converters (512, 513) connected to multiple bit lines, with a common current source (548) forming a current reference, and a common latching comparator (530). A column decode select circuit (515) which selects one of the multiple bit lines is interposed between the current-to-voltage converters (512, 513) and an input of the latching comparator (530). The distribution of the components of the sense amplifier (500) allows operation at low power supply voltages. The sense amplifier (500) uses a clamp and a loading device to establish a first discharge rate on a reference input of the latching comparator (530). The state of the selected memory cell establishes a second discharge rate on another input of the latching comparator (530), which is greater or less than the first discharge rate depending on the state of the memory cell. Portions of the comparator (530) also double as latches during a program mode.

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Nobukatua, Hiromi et al., "A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture," IEICE Trans. Electron, vol. E78-C. Jul. 7, 1995, pp. 818-824.

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