Semiconductor device using a chip scale package

Details Semiconductor device using a chip scale package Semiconductor device using a chip scale package

1998-11-05

2000-12-05

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257778, 257780, 257784, 257787, 257790, H01L 2352

Patent

active

06157080&

ABSTRACT:
A semiconductor device package which eliminates the possibility of damages to a solder connected portion of a flip-chip connected chip by load, or which eliminates ultrasonic output at the time of wire bonding is described. Electrodes of a first chip are connected to first connection pads corresponding to the electrodes with the first chip being bonded at its rear surface to a rear surface of a second chip. A first resin is interposed in a gap between the first chip and a circuit board so as not to cover the first or second connection pads. Thereafter, the electrode of the second chip is connected to the second connection pads by wires, and the whole device is overlayed by a second resin.

REFERENCES:
patent: 5008733 (1991-04-01), Mine et al.
patent: 5210938 (1993-05-01), Hirai
patent: 5385869 (1995-01-01), Liu et al.
patent: 5640052 (1997-06-01), Tsukamoto
patent: 5697148 (1997-12-01), Lance, Jr. et al.
patent: 5844320 (1998-12-01), Ono et al.
patent: 5889326 (1999-03-01), Tanaka

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