Method for making a CMOS circuit having a reduced tendency to la

Details Method for making a CMOS circuit having a reduced tendency to la Method for making a CMOS circuit having a reduced tendency to la

1984-09-06

1986-08-05

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576T, 148 15, 148187, 148DIG61, 357 2313, 357 91, H01L 21425, H01L 21265

Patent

active

046034714

ABSTRACT:
The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.

REFERENCES:
patent: 3796929 (1974-03-01), Nicholas et al.
patent: 4111719 (1978-09-01), Mader et al.
patent: 4498224 (1985-02-01), Maeguchi
patent: 4511408 (1985-04-01), Holonyak, Jr.
Yoshihiro et al., in Ion-Implantation in Semiconductors, ed. S. Namba, Plenum, N.Y. 1974, p. 571.
Stephen et al., Ibid, p. 619.
Nomura et al., Ibid, p. 681.

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