Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-06-19
1999-06-01
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
36518905, 36523008, 365218, G11C 1300
Patent
active
059093994
ABSTRACT:
The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
REFERENCES:
patent: 4279024 (1981-07-01), Schrenk
patent: 4597062 (1986-06-01), Asano et al.
patent: 4755970 (1988-07-01), Schrenk
patent: 4758988 (1988-07-01), Kuo
patent: 4763305 (1988-08-01), Kuo
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 4819212 (1989-04-01), Nakai et al.
patent: 4858192 (1989-08-01), Tatsumi et al.
patent: 4879689 (1989-11-01), Atsumi et al.
patent: 4881200 (1989-11-01), Urai
patent: 4881202 (1989-11-01), Tsujimoto et al.
patent: 4937787 (1990-06-01), Kobatake
patent: 4943948 (1990-07-01), Morton et al.
patent: 4972372 (1990-11-01), Ueno
patent: 5025418 (1991-06-01), Asoh
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5086413 (1992-02-01), Tsuboi et al.
patent: 5109257 (1992-04-01), Kondo
patent: 5109359 (1992-04-01), Sakakibara et al.
patent: 5124945 (1992-06-01), Schreck
patent: 5126973 (1992-06-01), Garcia et al.
patent: 5134583 (1992-07-01), Matsuo et al.
patent: 5136544 (1992-08-01), Rozman et al.
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5148398 (1992-09-01), Kohno
patent: 5153880 (1992-10-01), Owen et al.
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5172338 (1992-12-01), Mehrotra
patent: 5172339 (1992-12-01), Noguchi et al.
patent: 5233610 (1993-08-01), Nakayama
patent: 5299162 (1994-03-01), Kim et al.
patent: 5343437 (1994-08-01), Johnson et al.
patent: 5355340 (1994-10-01), Coker et al.
patent: 5361277 (1994-11-01), Grover
patent: 5428571 (1995-06-01), Atsumi et al.
patent: 5434819 (1995-07-01), Matsuo et al.
patent: 5483484 (1996-01-01), Endoh et al.
patent: 5513333 (1996-04-01), Kynett et al.
patent: 5537350 (1996-07-01), Larsen et al.
patent: 5566105 (1996-10-01), Tanaka et al.
patent: 5574684 (1996-11-01), Tomoeda
patent: 5574688 (1996-11-01), McClure et al.
M. Momodomi et al, A 4-Mb NAND EEPROM with Tight Programmed V.sub.t Distribution, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 492-495 Patent Abstracts of Japan, vol. 14, No. 381, Aug. 16, 1990, p. 1093.
Aritome Seiichi
Asano Masamichi
Itoh Yasuo
Iwata Yoshihisa
Kato Hideo
Fears Terrell W.
Kabushiki Kaisha Toshiba
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