PMOS memory array having OR gate architecture

Details PMOS memory array having OR gate architecture PMOS memory array having OR gate architecture

1997-10-09

1999-06-01

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518513, 36518517, 36518518, 36518529, G11C 1604

Patent

active

059093927

ABSTRACT:
A nonvolatile PMOS memory array includes a plurality of pages, where each column of a page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS OR string includes a PMOS select transistor coupled between the bit line and two series connected PMOS floating gate memory cells. The PMOS floating gate memory cells are programmed via channel hot electron (CHE) injection and erased via electron tunneling. A soft-program mechanism is used to compensate for over-erasing of the memory cells. In some embodiments, the bit lines are segmented along page boundaries to increase speed.

REFERENCES:
patent: 5365484 (1994-11-01), Cleveland et al.
patent: 5422843 (1995-06-01), Yamada
patent: 5581504 (1996-12-01), Chang
patent: 5796656 (1998-08-01), Kowshik et al.
patent: 5801994 (1998-09-01), Chang et al.

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