Planarization method for a semiconductor device

Details Planarization method for a semiconductor device Planarization method for a semiconductor device

1998-01-26

2000-09-12

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438710, 438712, 438720, H01L 213056

Patent

active

061177873

ABSTRACT:
A method of planarizing a multilayer semiconductor wiring structure includes the steps of forming a planarization layer on a substrate, forming a first conductive line pattern over the planarization layer, forming an insulation layer over the first conductive line pattern and the planarization layer, forming holes in the insulation layer to selectively expose portions of a top surface of the first conductive line pattern, forming a second conductive line pattern over the insulation layer, over portions of the first conductive line pattern, selectively in contact with the first conductive layer through the holes, and filling the holes, and forming a passivation layer over the second conductive line pattern, wherein conductive lines of the first conductive line pattern have a width of less than approximately 2 .mu.m.

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S. Bothra, et al.; "Integration of a 5-Level 0.35 .mu.m Backend Process Using HDP ECR Oxide"; DUMIC Conference Feb. 20-21, 1996; pp. 253-258.

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