Arithmetic unit and method for fourier transform

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G06F 1714

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058089250

ABSTRACT:
A Fourier transform arithmetic unit is reduced in cost and size by reducing the number of delay circuits. Data corresponding to each of input symbols is successively divided into quarters by a distribution switch. The first-quarter data is delayed by a delay circuit three times, that is, delayed by a total of 3N/4 (N: the number of data items of one symbol). The second-quarter data is delayed by a second delay circuit two times, that is, delayed by a total of N/2. The third-quarter data is delayed by N/4 by a third delay circuit. The fourth-quarter data is not delayed. These quarters of the input data are supplied to first to fourth input terminals of a butterfly operation device simultaneously with each other, data items in each quarter being input one after another. The butterfly operation device performs the butterfly operation using the data and outputs the operation result.

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Bidet et al., "A Fast Single-Chip Implementation of 8192 Complex Point FFT"; IEEE J. of Solid Date Circuits, vol. 30, No. 3, Mar. 1995, pp. 1666-1668.
Antola, "Multiple-Transform Pipelines for Image Coding: Structural Definition"; Signal Processing IV: 1988, pp. 1665-1668.

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