Decimating IIR filter

Details Decimating IIR filter Decimating IIR filter

1996-07-08

1998-09-15

Malzahn, David H.

Boots, shoes, and leggings

36472417, G06F 1710

Patent

active

058089241

ABSTRACT:
A first-order filter apparatus 48 (FIG. 4) includes an integrate-and-dump (I&D) circuit 50 and an output loop 52. The I&D circuit 50 is driven by a cyclic scaling element 54, which multiplies N consecutive input signals 56, x(m+1) to x(m+N), by a cycle of N scaling factors 58, c(1) to c(N). The I&D summer 60 drives a double-throw switch 62. The double-throw switch 62 applies the output of the I&D summer 60 to an I&D delay element 64 for N-1 input clock cycles, and for an Nth input clock cycle to the input of a non-cyclic scaling element 66. The non-cyclic scaling element 66 scales its input by a non-cyclic scaling factor, and applies its output to one input of a feedback summer 68. The output of the feedback summer 68 is y(k), the output of the apparatus. The index k advances by one every time that the index m advances by N. The output of the feedback summer 68 is also applied to an output feedback multiplying element 70, which multiplies it by B.sup.N. The output feedback multiplying element 70 applies its output to a feedback delay element 72, an output of which is applied to the other input of the feedback summer 68. Additional first-order (FIG. 4), and comparable second-order (FIG. 8), filter apparatus are weighted and summed to form a filter (FIG. 10).

REFERENCES:
patent: 4972356 (1990-11-01), Williams
patent: 5043933 (1991-08-01), Boutaud et al.
patent: 5339263 (1994-08-01), White
patent: 5689449 (1997-11-01), Saramaki et al.

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