Method of making a semiconductor integrated device having gate s

Details Method of making a semiconductor integrated device having gate s Method of making a semiconductor integrated device having gate s

1993-01-29

1994-08-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 48, 437919, H01L 2170, H01L 2700

Patent

active

053386990

ABSTRACT:
A method of making a semiconductor device including a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) are smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resist film in patterning the conductive interconnection layer.

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Wakamiya et al., "Novel Stacked Capacitor Cell for 64Mb DRAM", VLSI Technology Symposium (1989), pp. 69-70.

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