Semiconductor package and method of mounting the same on circuit

Details Semiconductor package and method of mounting the same on circuit Semiconductor package and method of mounting the same on circuit

1995-11-13

1998-09-15

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361748, 361751, 361764, 257684, 257690, 257780, 257784, H05K 114

Patent

active

058088725

ABSTRACT:
A semiconductor package includes a semiconductor chip having a plurality of electrodes on a main surface thereof, and a package substrate having first and second parallel surfaces, wherein the package substrate is fixed to the semiconductor chip in such a positional relationship that the main surface of the semiconductor chip faces the first surface, and has substantially the same size as a size of the semiconductor chip as viewed on a projection plane vertical to the first surface, and wherein the package substrate has a passage extending between the first and the second surfaces for electrically connecting the electrodes of the semiconductor chip to predetermined portions of the circuit board. A method of mounting the above-mentioned semiconductor package to the circuit board comprises electrically connecting the electrodes of the semiconductor chip to predetermined portions of the circuit board by bonding wires or bumps, through the passage provided to the semiconductor package.

REFERENCES:
patent: 4942454 (1990-07-01), Mori et al.
patent: 5594275 (1997-01-01), Kwon et al.
patent: 5627405 (1997-05-01), Chillara
Standards of Electronic Industries Association of Japan, ED-7402-1, General Rules For Preparation Of Outline Drawings Of Integrated Circuits, Small Outline Package, Feb. 1989.
Standards of Electronic Industries Association of Japan, ED-7402-4A, General Rules For The Preparation Of Outline Drawings Of Integrated Circuits Thin Small Outline Packages (Type II), Feb. 1990.

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