Method and apparatus for simultaneous address increment and memo

Details Method and apparatus for simultaneous address increment and memo Method and apparatus for simultaneous address increment and memo

1986-08-01

1989-05-09

Hecker, Stuart N.

Static information storage and retrieval

Plural shift register memory devices

36518905, 36518912, 36523008, 3652335, G11C 700, G11C 800

Patent

active

048294756

ABSTRACT:
A First-In First-Out (FIFO) shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A write address ring counter (32) is responsive to first transitions (164, 168) of a write pulses to increment to successive stages (32) therein. A plurality of latches (154) are each responsive to a second transition (166) to latch in a write address bit. The latches (154) are each enabled to write the address bit to a respective memory register (50) upon a successive first transition (168).

REFERENCES:
patent: 3896417 (1975-07-01), Beecham
patent: 3953838 (1976-04-01), Gilberg et al.
patent: 4090256 (1978-05-01), Hepworth et al.
patent: 4151609 (1979-04-01), Moss
patent: 4156288 (1979-05-01), Spandorfer
patent: 4525849 (1985-06-01), Wolf

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