Semiconductor memory system

Details Semiconductor memory system Semiconductor memory system

1995-06-07

1997-01-28

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518509, 36518907, 365200, 371 103, G11C 700, G11C 800, G11C 1134, G11C 2900

Patent

active

055983731

ABSTRACT:
A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.

REFERENCES:
patent: 4628509 (1986-12-01), Kawaguchi

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