Boots – shoes – and leggings
Patent
1994-07-22
1997-01-28
Teska, Kevin J.
Boots, shoes, and leggings
364490, 364489, 364488, 327565, 257202, 257368, 257377, 257206, 36518901, 36518908, 326 38, 326 39, 326 88, 326113, G06F 1500, H01L 2710
Patent
active
055983472
ABSTRACT:
An integrated circuit device is provided, in which optimization design can be made for a short term to suppress power consumption of the integrated circuit device and improve the maximum operation frequency. First basic cells and second basic cells are disposed in a first direction. The second basic cells are the same in circuit function other than load driving capability as the first basic cells and the same in the cell width in the first direction and relative positions of input and output terminals. The first and second basic cells preferably contain MOS transistors, respectively, whose gate widths in the direction perpendicular to the cell width are made different from each other.
REFERENCES:
patent: 4622648 (1986-11-01), Whitaker
patent: 4663646 (1987-05-01), Ikawa et al.
patent: 4839710 (1989-06-01), Holzapfel et al.
patent: 4855954 (1989-08-01), Turner et al.
patent: 4896296 (1990-01-01), Turner et al.
patent: 4899309 (1990-02-01), Kitazawa et al.
patent: 4949275 (1990-08-01), Nonaka
patent: 5060046 (1991-10-01), Shintani
patent: 5119313 (1992-06-01), Shaw et al.
patent: 5150309 (1992-09-01), Shaw et al.
patent: 5282148 (1994-01-01), Poirot et al.
patent: 5300790 (1994-04-01), Hirabayashi et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5311443 (1994-05-01), Crain et al.
patent: 5369595 (1994-11-01), Gould et al.
patent: 5388054 (1995-02-01), Tokumaru
patent: 5388055 (1995-02-01), Tanizawa et al.
Hurst, Stanley L., Custom VLSI Microelectronics, Jan. 1992, Prentice Hall International; Cambridge, UK pp. 116-127.
Louis-Jacques Jacques
NEC Corporation
Teska Kevin J.
LandOfFree
Layout method for designing an integrated circuit device by usin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Layout method for designing an integrated circuit device by usin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout method for designing an integrated circuit device by usin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-945371