Method of segmenting an FPGA channel architecture for maximum ro

Details Method of segmenting an FPGA channel architecture for maximum ro Method of segmenting an FPGA channel architecture for maximum ro

1993-10-01

1997-01-28

Trans, Vincent N.

Boots, shoes, and leggings

326 39, 326 41, 34082583, H03K 19177, H03K 17693

Patent

active

055983430

ABSTRACT:
The current invention considers automatic synthesis of segmented channel architecture of row-based FPGAs so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A simulated annealing based channel architecture synthesis algorithm has been developed which enhances routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance.

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