Multiplex communications – Wide area network – Packet switching
Patent
1990-04-26
1991-05-07
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370102, 3701001, 375112, H04J 306
Patent
active
050142704
ABSTRACT:
A synchronizing device synchronizes a pseudo-binary signal particularly affected by high jitter with a regenerated clock signal into a synchronized signal. The device can be included between an output of a bipolar-to-binary converter receiving a plesiochronous bipolar signal and an input of a HDB/binary transcoder in a synchronizing circuit of a time-division multiplexer. The clock signal has a period Tj substantially lower than the nominal period of the pseudo-binary signal and offers phase jumps, particularly included between Tj/2 and Tj, for the clock signal to have a mean period equal to the nominal period. The device preferably comprises, on the input side, a flip-flop used as a divide-by-2 frequency divider for providing a first logic signal alternately having logic levels "0" and "1" in response to transitions "0" to "1" in the pseudo-binary signal, then a second flip-flop for phasing the transitions in the first logic signal with active transitions "0" to "1" of the clock signal thereby deriving a phased logic signal, and two flips-flops and a Exclusive-OR gate for supplying the synchronized signal with pulses which are at level "1" and which have a width calibrated as a function of the period of the clock signal and which are respectively derived in response to the transitions of the phased signal.
REFERENCES:
patent: 3919647 (1975-11-01), Haass
patent: 3980820 (1976-09-01), Niemi
patent: 4119796 (1978-10-01), Jones
patent: 4408333 (1983-10-01), Fujii
patent: 4569063 (1986-02-01), Perry
patent: 4669080 (1987-05-01), Aveneau et al.
patent: 4821296 (1989-04-01), Cordell
Kizou H.
Olms Douglas W.
SAT (Societe Anonyme de Telecommunications
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