Dynamic semiconductor memory device having reduced soft error ra

Details Dynamic semiconductor memory device having reduced soft error ra Dynamic semiconductor memory device having reduced soft error ra

1989-04-12

1991-05-07

Fears, Terrell W.

Static information storage and retrieval

Format or disposition of elements

365 63, 365202, G11C 502, G11C 506, G11C 700

Patent

active

050142410

ABSTRACT:
Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.

REFERENCES:
patent: 4367540 (1983-01-01), Shimohigashi
patent: 4586171 (1982-05-01), Fujishima
patent: 4792928 (1988-12-01), Tobita
patent: 4800525 (1989-01-01), Shah et al.
patent: 4872142 (1989-10-01), Hannai
T. Yoshira, "A Twisted Bit Line Technique for Multi-Mb Drams", 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (Feb. 19, 1988, pp. 238-239.

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