Input/output bus expansion interface

Details Input/output bus expansion interface Input/output bus expansion interface

1988-01-29

1991-05-07

Shaw, Gareth D.

Boots, shoes, and leggings

36492793, 36492799, 364941, G06F 300, G06F 1312, G06F 1332

Patent

active

050142364

ABSTRACT:
An I/O bus expansion interface is disclosed which enables an I/O device having an n-bit data bus to be interfaced to an m times n-bit I/O data bus of a host processor. This I/O bus expansion circuit maximizes the computer processor's performance by providing full I/O data bus bandwidth and allowing overlap of processor execution and I/O bus expansion interface circuit operation. This is accomplished by: (1) prefetching multiple control and/or data fields from the I/O device and presenting that information to the host without delay and (2) burst writing multiple fields from the host to the bus expansion interface circuit, without delay of the host, and thereafter making these fields individually available to the I/O device.

REFERENCES:
patent: 3725864 (1973-04-01), Clark et al.
patent: 4417303 (1983-11-01), Korowitz et al.
patent: 4447878 (1984-05-01), Kinnie et al.
patent: 4716527 (1987-12-01), Graciotti
patent: 4727477 (1988-02-01), Gavril
IBM Technical Disclosure Bulletin, vol. 14, No. 3, Aug. 1971, pp. 799-800, R. A. Palm et al, "I/O Channel for Computer".
IBM Technical Disclosure Bulletin, vol. 26, No. 10A, Mar. 1984, pp. 5199-5206, S. E. Edick, "Direct Memory Access Controller".
IBM Technical Disclosure Bulletin, vol. 30, No. 6, Nov. 1987, pp. 205-207, "Eight-Bit to Sixteen-Bit Memory Converter".

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