Programmable voltage offset circuit

Details Programmable voltage offset circuit Programmable voltage offset circuit

1987-11-23

1989-05-09

Smith, Jerry

Boots, shoes, and leggings

36457105, 36457101, G06J 100, G06F 1100, H03K 520

Patent

active

048294594

ABSTRACT:
A programmable voltage offset circuit (PVOC) (1) comprises a temporary latch memory (7); a latch disable circuit (5) which selects that PVOC (1) among several such circuits which may be simultaneously present on the same semiconductor chip; a resistor array (3); and a programmable nonvolatile memory (37). The desired voltage offsets V(OFFSET)s are temporarily produced in an iterative manner using the latch memory (7). Quasi-permanent voltage offsets V(OFFSET)s are then programmed using the nonvolatile memories (37), each of which typically comprises an EPROM (39). Application of an avalanche voltage V(STORE) to a PFET (43) portion of the EPROM (39) causes the PFET (43) to avalanche, thereby selectively programming the nonvolatile memory (37), depending upon the status of a signal supplied from the latch memory (7).

REFERENCES:
patent: 3721838 (1973-03-01), Brickman et al.
patent: 4050030 (1977-09-01), Russell
patent: 4159523 (1979-06-01), Neet
patent: 4245165 (1981-01-01), Hoffman
patent: 4412241 (1983-10-01), Nelson
patent: 4482967 (1984-11-01), Evans, Jr. et al.
patent: 4573144 (1986-02-01), Countryman, Jr.
IBM Technical Disclosure Bulletin, vol. 19, No. 8, Jan. 1977, "Fusible Link Device", by L. Ewald et al.

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