Adapting device for accommodating different memory and bus forma

Details Adapting device for accommodating different memory and bus forma Adapting device for accommodating different memory and bus forma

1988-05-13

1991-05-07

Chan, Eddie P.

Boots, shoes, and leggings

3642523, 3642526, 364239, 3642393, G06F 1200

Patent

active

050141872

ABSTRACT:
Disclosed is a memory access control device for a memory organized in 2.sup.n byte words and having the capability of addressing each byte in a word under control of byte select signals (BS), through an m-byte wide bus 22, with 2.sup.n /m being an integer k, to write or read data byte bursts comprising a variable count of bytes. For writing, k sets of m bytes received from bus 22 are stored into 2.sup.n registers 40 during each bus period T; they are then transferred into buffer 30 which comprises successive location of 2.sup.n bytes positions, through an alignment and control logic 42, which causes the buffer to be written in such a way that it maps the data arrangement in memory. This depends upon the least significant bits of the memory starting address determining the byte location within the memory words. Once the complete data burst is written into the buffer, the buffer content is transferred to the memory.

REFERENCES:
patent: 3916388 (1975-10-01), Shimp et al.
patent: 4131940 (1978-12-01), Moyer
patent: 4631671 (1986-12-01), Kawashita
patent: 4654781 (1987-03-01), Schwartz et al.
IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986, pp. 864-868, Armonk, N.Y., U.S.: "Hardware-Assisted Byte Alignment for High-Speed Digital Communications Processors", FIGS. 1-5; p. 865, Lines 3-7; p. 866, Lines 5-12, Lines 5-12, p. 867, Lines 1-7.

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