Multiplexing decoder/counter circuit for monitoring quadrature p

Details Multiplexing decoder/counter circuit for monitoring quadrature p Multiplexing decoder/counter circuit for monitoring quadrature p

Filed on

1997-09-22

Date issued

2000-02-01

Examiner

Wells, Kenneth B.

Patent Class

Electrical pulse counters, pulse dividers, or shift registers: c

SubClass

Applications

SubSubClass

Determining machine or apparatus operating time or...

Other Related Categories

377 49, 318565, G07C 300

Type

Patent

Status

active

Patent number

060211717

Description

ABSTRACT:
A multiplexing decoder/counter circuit for monitoring quadrature position encoders. The system includes an edge detector, a position counter, a position latch, a capture latch, and compare management means. Addressable memory blocks are used throughout the design. Information from external differential receivers is directed into a single quadrature decoder circuit using a switch with an effective 16 to 1 selection. An axis scanning state machine addresses multiple memory block based functions simultaneously. Scanning is performed in a circuitous manner in conjunction with the switch. The total circular loop frequency for the sequence is chosen to be equal to or greater than the maximum encoder frequency required. At each visitation of any particular memory address, the state of the circuit is reestablished from the last visit by the scanning state machine. Any change in quadrature signals is noted, and any up or down count is accumulated to the position counter. This information is then stored back into memory and the system moves to the next memory location. The compare management information goes through a steering switch into a series of non-multiplexed compare latches to sustain hardware outputs even when a particular axis is not being selected. Each memory location in the control system corresponds to an independent motor.

REFERENCES:
patent: 5684374 (1997-11-01), Chaffee

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