Bit latch scheme for parallel program verify in floating gate me

Details Bit latch scheme for parallel program verify in floating gate me Bit latch scheme for parallel program verify in floating gate me

1998-09-24

2000-02-01

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518905, 36518512, G11C 1606

Patent

active

060210699

ABSTRACT:
A method for determining successful programming of a set of memory cells in an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array, and bit latches coupled to the respective bit lines. The method includes applying a word line voltage to a word line across which memory cells in the set of memory cells are accessible. A potential applied to memory cells in the set of memory cells is raised. A current load is caused from the bit line. Changes in respective voltage levels of bit lines in the set of bit lines are responded to in parallel to store a constant in bit latches in the set of bit latches coupled to bit lines on which the respective voltage levels pass a determinate threshold during the step of applying a word line voltage. An integrated circuit memory is described. The memory includes a device, connected to a bit line and ground, for selectively causing a current flow from the bit line at least before loading a constant into the memory element.

REFERENCES:
patent: 5379256 (1995-01-01), Tanaka et al.
patent: 5835414 (1998-11-01), Hung et al.
patent: 5909399 (1999-06-01), Tanaka et al.

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