Clockless A/D converter

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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Details

341158, H03M 142

Patent

active

050140574

ABSTRACT:
An analog-to-digital converter circuit receives an input signal of a first polarity and a reference voltage of a second polarity. The circuit has a first binary comparator with a resistor divider network connected between the input signal and the reference voltage. The first stage provides a most significant bit signal in response to the absolute value of the input signal exceeding one half the absolute value of the reference voltage. The circuit has at least a second binary bit stage. Each successive binary stage is responsive to the signal voltage and to the logic binary value of all higher order stages. The first and subsequent binary stage provides a binary coded signal with a value corresponding to the ratio of the value of input signal with respect to the value of the reference voltage. The first and second binary stages each have a binary comparator with a first polarity input connected to a reference potential. The first and second binary stages also have a second polarity input, and an output terminal. Each stage has a divider with a first and second resistor. Each resistor has a first and second terminal. The second resistor of each divider has a resistance substantially equal to one half the value of the first resistor. The first resistor first terminal of each divider is connected to the reference voltage. The second resistor first terminal of each divider is connected to the input signal. The first and second resistors' second terminals of each respective divider are common and are connected to the respective comparator second polarity input.

REFERENCES:
patent: 3638218 (1972-01-01), Kaneko et al.
patent: 4306224 (1981-12-01), Geller et al.
patent: 4769628 (1988-09-01), Hellerman
patent: 4771266 (1988-09-01), Nurokawa

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