Single-side oxide sealed salicide process for EPROMs

Details Single-side oxide sealed salicide process for EPROMs Single-side oxide sealed salicide process for EPROMs

1995-12-20

1997-01-28

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 49, 437200, H01L 218247

Patent

active

055977510

ABSTRACT:
A method of forming a memory cell structure in a semiconductor substrate that does not have a shorting problem between a floating gate and a source/drain region of the substrate by depositing a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness such that electrical insulation is provided thereinbetween to prevent the occurrence of a short or the formation of a silicide bridge. The invention is also directed to a semiconductor device fabricated by the method.

REFERENCES:
patent: 5330938 (1994-07-01), Camerlenghi
patent: 5364806 (1994-11-01), Ma et al.
patent: 5494838 (1996-02-01), Chang et al.

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