Fishing – trapping – and vermin destroying
Patent
1994-05-23
1997-01-28
Niebling, John
Fishing, trapping, and vermin destroying
437 52, H01L 218247
Patent
active
055977480
ABSTRACT:
The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
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Asano Masamichi
Endoh Tetsuo
Inoue Satoshi
Iwahashi Hiroshi
Kirisawa Ryouhei
Booth Richard A.
Kabushiki Kaisha Toshiba
Niebling John
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