Fishing – trapping – and vermin destroying
Patent
1995-03-06
1997-01-28
Niebling, John
Fishing, trapping, and vermin destroying
437 46, 437 47, 437 57, 437 69, 437 71, 437 62, 437101, 437187, 437239, 148DIG150, 148DIG152, H01L 21265
Patent
active
055977383
ABSTRACT:
A method for fabricating a single crystal silicon on insulator material by forming oxidized layers underneath epi islands without damaging the surface quality of the silicon. In an illustrative embodiment, an epitaxial layer of p-type silicon is grown on a substrate of n-type silicon. A plurality of islands are defined from the epitaxial layer. A semiconductor device is fabricated from one of the p-islands by electrochemically anodizing a region of the substrate beneath that p-island, which p-island can be used to fabricate a selected semiconductor device. If n-type material is required for device fabrication, a device layer of n-type silicon can be grown on the surface of a p-islands and that p-island can be anodized and oxidized to form the insulating layer between the device layer and substrate. In this manner, MOS transistors and other devices may be fabricated for operation at temperatures of up to 500.degree. C.
REFERENCES:
patent: 4104090 (1978-08-01), Pogge
patent: 4143177 (1979-03-01), Kovac et al.
patent: 4393577 (1983-07-01), Imai
patent: 4532700 (1985-08-01), Kinney et al.
patent: 4628591 (1986-12-01), Zorinsky et al.
patent: 4716128 (1987-12-01), Schubert et al.
patent: 4910165 (1990-03-01), Lee et al.
patent: 5023200 (1991-06-01), Blewer et al.
patent: 5100810 (1992-03-01), Yoshimi et al.
patent: 5298767 (1994-03-01), Shor et al.
patent: 5466631 (1995-11-01), Ichikawa et al.
"Very Thin Silicon-on-Insulator Devices for CMOS at 500.degree. C.", by John B. McKitterick, pp. 37-41, Jul. 1993.
Kurtz Anthony D.
Ned Alexander A.
Shor Joseph S.
Kulite Semiconductor Products Inc.
Niebling John
Pham Long
LandOfFree
Method for forming isolated CMOS structures on SOI structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming isolated CMOS structures on SOI structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming isolated CMOS structures on SOI structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-941004