Boots – shoes – and leggings
Patent
1987-12-16
1991-01-08
Lee, Thomas C.
Boots, shoes, and leggings
364950, 364951, 3649503, 375106, G06F 1500, G06F 112
Patent
active
049841947
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The invention relates to a method of transferring data words in parallel form from a transmitter register to a receiver register between transmitting equipment having a first independent clock and receiving equipment having a second independent clock. The invention also relates to an apparatus for carrying out the method.
DESCRIPTION OF RELATED ART
In both large and small digital systems there is a need of transferring information between units which are driven by independent clocks. This information may signify an order to step an error counter, a request for entry into a memory or to transfer 8-bit parrallel data to peripheral equipment driven by a clock independent of the transmitting unit. The task of the receiving unit can be to convert data obtained in parallel form to series data for linking in as PCM data in a PCM system. For example, in a practical case equipment having a 5 MHz clock on the transmitter side is co-operating with equipment having a 2 MHz clock on the receiver side.
Difficulties will occur at the interface between the transmiting and receiving equipment, particularly when both equipments are driven by synchronous logic, i.g. when all state changes in the memory units included in counter, register, flip-flops etc., take place with the equipment's own system clock.
The simplest method for transferring in the cases discussed is that the data information on the receiver side is fed into a register with the aid of a write pulse coming from the transmitter side. This pulse must be adapted to the clock frequency on the receiver side such that it is just as long as the receiver side clock period. This signifies that the clock frequencies cannot be changed independently of each other. Lowering the reception side clock frequency, i.e. extending the clock period to twice its length, for example, results in the need of changing the write pulse from the transmitter side in a corresponding manner, in turn resulting in the necessity of altering the transmitter side components.
SUMMARY OF THE INVENTION
The disadvantage just mentioned is eliminated by the invention, it not being necessary to alter the transmission side clock frequency if an alteration of the receiver side clock frequency becomes necessary, since the write pulse is generated on the receiver side and its length is determined by the receiver side clock period.
The invention is characterized by the disclosures in the claims.
BRIEF DESCRIPTION OF DRAWINGS
The invention will now be described in detail below with the aid of an embodiment and with reference to the accompanying drawing, on which
FIG. 1 schematically illustrates two coacting data processing units, the invention being applied at the interfaces of these units,
FIG. 2 illustrates two units having their own clocks, the units co-acting with each other across an interface in a conventional manner,
FIGS. 3a-3h represent a pulse diagram of the function of the apparatus according to FIG. 2,
FIG. 4 illustrates an apparatus operating according to the inventive principle and
FIGS. 5a-5j illustrates the pulse diagram of the function of the device according to FIG. 4.
DESCRIPTION OF PREFERRED EMBODIMENTS
FIG. 1 is a block diagram of a system where the invention is applied. A computer DA is in communiction with remaining unillustrated means and a first interface unit E1 via a bus system BU. The interface unit E1 is in communication via an 8-wire line with a second interface unit E2 on the receiver side for transferring parallel data words. The receiver unit E2 sends data words in series form to a PCM system. The interface units E1 and E2 are each driven by their respective clock signals CL1 and CL2.
FIG. 2 illustrates the interface units E1 and E2 in the form of a block diagram. A register REG 1 on the transmitter side is built up from 8 flip-flops which can be fed with an 8-bit information word via the inputs IN 1-8 when a feed signal LO1 simultaneously occurs with the trailing edge of the clock signal CL1 on the inputs of the register flip-flops. A contr
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patent: 4607348 (1986-08-01), Sheth
patent: 4621341 (1986-11-01), New
patent: 4787064 (1988-11-01), Wagner
Lee Thomas C.
Telefonaktiebolaget L M Ericsson
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