MOS transistors using selective polysilicon deposition

Details MOS transistors using selective polysilicon deposition MOS transistors using selective polysilicon deposition

1989-02-13

1991-01-08

Wojciechowicz, Edward J.

357 2311, 357 59, 357 89, H01L 2978

Patent

active

049840428

ABSTRACT:
In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

REFERENCES:
Tsang-IBM TDB, vol. 25, No. 1, Jun. 1982, pp. 365-366, "Process for FET with Short Channel Defined by Shallow-Extensions of Drained Source".
Esnault et al.-IBM TDB, vol. 16, No. 5, Oct. 1973, pp. 1498-1999, "Self-Aligned Insulated Gate Field-Effect Transistor".
IBM TDB,-vol. 27, No. 10A, Mar. 1985, pp. 5699-5700, "Full LDD Devices Fabricated by Photoresist Plavarization".

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