Memory write error detection circuit

Details Memory write error detection circuit Memory write error detection circuit

1980-03-31

1981-10-13

Atkinson, Charles E.

Excavating

364900, G06F 1110

Patent

active

042952190

ABSTRACT:
A circuit for the detection of write errors in a memory with selectable byte addressing. The memory is capable of selectively writing bytes within a memory word by decoding control signals and address signals received from a processor. The decoder and transmission path of the control signals are checked by the processor generating incorrect parity for the bytes which are not to be written. The memory decodes the control signals, checks the parity of the bytes, and generates a write parity error if the decoder selects a byte with incorrect parity to be written. If the memory malfunctions and spuriously writes an unselected byte, this fact will be detected when the unselected byte is read. The memory checks each byte read for parity, and incorrect parity causes the memory to transmit a read memory error to the processor.

REFERENCES:
patent: 3992696 (1976-11-01), Fergeson
patent: 4045781 (1977-08-01), Levy et al.
patent: 4050059 (1977-09-01), Williams et al.

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