Vertical DMOS transistor fabrication process

Details Vertical DMOS transistor fabrication process Vertical DMOS transistor fabrication process

1988-12-28

1991-01-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 38, 437 41, 437179, 437192, 437201, 437203, 437 44, 148DIG105, 148DIG126, 357 234, H01L 21335

Patent

active

049835351

ABSTRACT:
A process for fabricating a vertical DMOS transistor is set forth. The starting material is a heavily doped silicon wafer which has an epitaxial layer thereon. A DMOS body region is diffused into the epitaxial layer and a deep body contact region created. The source is a refractory metal Schottky barrier located on top of the body region. A trench is etched into the epitaxial layer so as to fully penetrate the body region and the trench surfaces oxidized to form a gate oxide. The trench is then filled with doped polysilicon to create a gate electrode. The resulting DMOS has a relatively short channel and the parallel bipolar parasitic transistor cannot be turned on.

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Y. Pauleau, "Interconnect Materials for VLSI Circuits", Solid State Technology, Apr. 1987, pp. 155-162.

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