Storage transistor

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357 23, 357 41, H01C 2978, G11C 1140

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042951500

ABSTRACT:
A storage transistor includes a semiconductor substrate having formed therein a source region and a drain region spaced from said source region forming a channel region therebetween. A gate electrode is disposed over said channel region and a layer of storage medium has a first portion extending between the channel region and the gate electrode and a second portion extending laterally outside from between the channel region and the gate electrode, the ratio of the area of the second portion to the area of the first portion being in the range of 2 to 3. A first partial gate insulator layer is disposed between the channel region and the layer of storage medium and has a thickness ranging between 100 and 200 A.U., while a second partial gate insulator layer is disposed between the layer of storage medium and the gate electrode and has a thickness in the range of between 200 and 500 A.U. Whereby an erase or write pulse may be applied to the gate electrode for storing or removing a charge into or from the storage medium respectively and thereby displacing the threshold voltage and a read pulse may be applied to the gate electrode for scanning the magnitude of the threshold voltage.

REFERENCES:
patent: 4115914 (1978-09-01), Harari
patent: 4162504 (1979-07-01), Hsu
IEEE Trans. on Electron Devices, vol. ED. 24, No. 5, May 1977, pp. 600-610.

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