Nonvolatile electrically alterable memory and method

Details Nonvolatile electrically alterable memory and method Nonvolatile electrically alterable memory and method

1985-07-22

1988-06-21

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

357 235, G11C 1134

Patent

active

047529121

ABSTRACT:
A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described as including four electrode layers, one of which being formed as a substrate coupling electrode. The cell is also described as being relatively process intolerant. The first electrode layer above the substrate is used to mask the diffusion or implantation of the substrate coupling electrode and other regions in the substrate to form self-aligned active devices.

REFERENCES:
patent: 4274012 (1981-06-01), Simko
patent: 4300212 (1981-11-01), Simko
patent: 4314265 (1982-02-01), Simko
patent: 4486769 (1984-12-01), Simko
patent: 4599706 (1986-07-01), Guterman

Affiliated with

Also associated with

Rating

Nonvolatile electrically alterable memory and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile electrically alterable memory and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile electrically alterable memory and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-933664