Memory system employing a low DC power gate array for error corr

Details Memory system employing a low DC power gate array for error corr Memory system employing a low DC power gate array for error corr

1986-03-03

1988-01-12

Fleming, Michael R.

Excavating

371 13, G06F 1100

Patent

active

047196270

ABSTRACT:
An error-correcting memory system includes a storage module which receives an address during a read cycle and which reads data bits and check bits at the address, and it further includes a low DC power logic circuit which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the logic circuit is comprised of: a plurality of logic gates, one for generating each of the minterms by passing a constant power dissipating current to selectively decode the check bits; a control circuit for generating a control signal that is in one state during only a small fraction of the read cycle and is otherwise in an opposite state; and an enabling circuit, coupled between the control circuit and the logic gates, for enabling their selective decoding by permitting the constant current to flow through the gates only while the control signal is in its one state.

REFERENCES:
patent: 4394763 (1983-07-01), Nagano
patent: 4456996 (1984-06-01), Haas
patent: 4593393 (1986-06-01), Mead
patent: 4641310 (1987-02-01), Martens
patent: 4646304 (1987-02-01), Fossati

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