Drive circuit comprising a subsidiary drive circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307445, 307448, 307443, H03K 19094

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active

051665557

ABSTRACT:
In a driving circuit supplied with an input signal having one of logic one and zero levels and producing an output signal through an output terminal to drive a load circuit connected to the output terminal, a first MOS transistor (26) is put into a first source-drain conductive state to produce a predetermined positive voltage (VDD) as the output signal when the input signal has the logic one level. The first MOS transistor has a first channel between its source and drain terminals. A second MOS transistor (27) is put into a second source-drain conductive state to produce a ground potential as the output signal when the input signal has the logic zero level. The second MOS transistor has a second channel between its source and drain terminals. Each of the first and the second channels has a restricted channel width to restrict source-drain currents flowing through the first and the second channels. A subsidiary drive circuit (30) drives the load circuit during transition time interval each time when the input signal changes from one of the logic one and zero levels to another of the logic one and zero levels.

REFERENCES:
patent: 4948990 (1990-08-01), Shin et al.
patent: 4987324 (1991-01-01), Wong et al.
patent: 5003205 (1991-03-01), Kohda et al.
patent: 5023472 (1991-06-01), Hashimoto et al.
patent: 5030860 (1991-07-01), Tran
patent: 5079439 (1992-01-01), Wanlass

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