Process for fabricating a silicon on insulator field effect tran

Details Process for fabricating a silicon on insulator field effect tran Process for fabricating a silicon on insulator field effect tran

1991-09-03

1992-11-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 29, 437234, 437913, 437131, 148DIG150, H01L 21265

Patent

active

051660849

ABSTRACT:
A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).

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"Selective Etching of SiGe on SiGe/Si Heterostructures," by G. K. Change et al., Journal of the Electrochemical Society, vol. 138, No. 1, Jan. 1991, pp. 202-204.

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