Method for preventing latchup in CMOS devices

Details Method for preventing latchup in CMOS devices Method for preventing latchup in CMOS devices

1987-03-02

1988-08-09

Roy, Upendra

Fishing, trapping, and vermin destroying

148DIG82, 357 42, 357 91, 437 26, 437 29, 437 34, H01L 21265, H01L 2138

Patent

active

047628022

ABSTRACT:
The present invention relates to a CMOS structure, and method for forming the same, which prevents latchup in MOS devices. The method is directed to the CMOS structure and functions to reduce the lateral resistance of the n-tub, where the presence of a large lateral resistance in the n-tubs of prior art arrangements, has been found to cause latchup. A retrograde n.sup.+ region is formed at a predetermined location in the n-tub using proton bombardment to increase the n-type donor concentration at this predetermined location in the n-tub and thus significantly reduce the lateral resistance associated with the n-tub. By reducing this resistance, the parasistic SCR action between the two types of bipolar devices will be lessened, since the lower resistance of the n-tub reduces the IR drop associated with the parasitic device located in the n-tub. A beam of hydrogen ions, or doubly ionized helium, is used as the proton source. The n.sup.+ region bmay be formed subsequent to the formation of the CMOS transistor diffusion regions, thus providing a method of decreasing the n-tub lateral resistance without interfering with the conventional CMOS processing steps.

REFERENCES:
patent: 4161417 (1979-07-01), Yim et al.
patent: 4203126 (1980-05-01), Yim et al.
patent: 4288804 (1981-09-01), Kikuchi et al.
patent: 4302875 (1981-12-01), Satou et al.
patent: 4318750 (1982-03-01), Rai-Choudhury et al.
patent: 4320409 (1982-03-01), Shoji
patent: 4327368 (1982-04-01), Uchida
patent: 4506436 (1985-03-01), Bakeman, Jr. et al.
patent: 4567713 (1986-05-01), Goodman et al.
patent: 4619033 (1986-10-01), Jastrzebski
patent: 4637125 (1987-01-01), Iwasaki et al.
Chao et al., IBM-TDB, 25 (1982), 3350.
"Electrical Properties of n-Type . . . ", Solid State Communications, Nov. 1972, Y. Ohmura et al., pp. 263-265.
"Shallow Donor Formation . . . ", Phys. Stat. Sol. (a), vol. 15, 1973, Y. Ohmura et al., pp. 93-98.
"Latchup Control in CMOS . . . ", IEEE Trans. in Nuclear Science, vol. NS-26, No. 6, Dec. 1979, A Ochoa et al., pp. 5056-5058.
Elimination of Latchup . . . ", IEDM '80, Dec. 8-10, 1980, R. S. Payne et al., pp. 248-251.
"A Retrograde p-Well . . . ", IEEE Trans. on Electron Devices, vol. ED-28, No. 10, Oct. 1981, R. D. Rung et al, pp. 1115-1119.
"Scaleable Retrograde P-Well . . . ", IEDM'81, Dec. 7-9, 1981, S. R. Combs, pp. 346-349.
"Latchup Prevention Using an N-Well . . . ", IEEE Trans. on Electron Devices, vol. ED-30, No. 10, Oct. 1983, P. J. Holly et al., pp. 1403-1405.
"Full Isolation Technology . . . ", IEDM '81, Dec. 7-9, 1981, K. Imai et al., pp. 376-379.
"Characterization of CMOS Latchup", IEDM '82, Dec. 13-15, 1982, C. C. Huang et al., pp. 454-457.

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