Multilayer wiring technique for a semiconductor device

Details Multilayer wiring technique for a semiconductor device Multilayer wiring technique for a semiconductor device

1989-02-03

1989-09-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437190, 437192, 437195, 437 10, 357 71, 148DIG50, 148DIG60, H01L 2144

Patent

active

048660094

ABSTRACT:
A method of manufacturing a semiconductor device includes the steps of (a) forming a first conductive pattern on a semiconductor substrate, (b) forming a first interlayer insulating film, covering the first conductive pattern, (c) forming a second conductive pattern, composed of a refractory metal, on the first interlayer insulating film, (d) forming a contact hole reaching the first conductive pattern through the second conductive pattern and the first interlayer insulating film at a predetermined position, (e) performing an annealing step before or after formation of the contact hole in step (d), and (f) covering in the contact hole with a metal film, after annealing step (e), to connect the second conductive pattern to the first conductive pattern. In this method, annealing step--for example, gettering--is performed before the wiring layer of the refractory metal is placed in contact with the semiconductor layer. For this reason, even if the other semiconductor layers are made of silicon, silicification of the refractory metal can be prevented.

REFERENCES:
patent: 3323198 (1967-06-01), Shortes
patent: 3382568 (1968-05-01), Kuiper
patent: 4184909 (1980-01-01), Chang et al.
patent: 4265935 (1981-05-01), Hall
patent: 4536949 (1985-08-01), Takayama et al.
patent: 4619037 (1986-10-01), Taguchi et al.

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