Process for formation of capacitor for DRAM cell

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 218242

Patent

active

055019994

ABSTRACT:
A DRAM cell and a process for formation of a capacitor of a DRAM cell. The present invention provides a lower plate electrode consisting of a first conductive layer formed upon a first inter-layer insulating layer, the first inter-layer insulating layer covering the cell region except a contact hole portion; a capacitor dielectric layer formed on the surface of the lower plate electrode; a capacitor lower node electrode consisting of a second conductive layer formed on the dielectric layer and contacting with the source of a pass transistor; a bit line layer disposed upon a second insulating layer and connected to the drain region of the pass transistor through the second inter-layer insulating layer (disposed upon the lower node electrode); a capacitor upper node electrode consisting of a third conductive layer and connected to the capacitor lower node electrode after passing through the second inter-layer insulating layer and through a fourth insulating layer (disposed upon the bit line layer); a capacitor dielectric layer formed upon the capacitor upper node electrode; and a capacitor upper plate electrode consisting of a fourth conductive layer formed on the dielectric layer.

REFERENCES:
patent: 5006481 (1991-04-01), Chan et al.
patent: 5114873 (1992-05-01), Kim et al.
patent: 5162249 (1992-11-01), Kim
patent: 5227322 (1993-07-01), Ko et al.
patent: 5270238 (1993-12-01), Kim

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