Variable radix processor

Details Variable radix processor Variable radix processor

1982-11-16

1985-07-09

Malzahn, David H.

Boots, shoes, and leggings

364736, 364749, G06F 752

Patent

active

045286418

ABSTRACT:
A variable radix processor is constructed on 1.25 micrometer CMOS/SOS. The processor, based upon a predetermined algorithm, is constructed to process radix 2 to 7 data wherein the data is input in a parallel-by-word, parallel-by-bit format. A format selection switch has the data input whereafter a plurality of switches outputs an address format to a bit-slice multiply-adder. The bit slice multiply-adder has ROMs addressed by the format selection switch. Based upon the predetermined algorithm, each unique address format causes the ROMs to output a unique word in parallel bits to a tally cascade circuit and then to a fast-carry adder. The processor can operate on a transfer function such as Z.sub.A =.+-.(A.+-.C), Z.sub.B =B where A=.SIGMA.a.sub.i X.sub.i, B=b.sub.i X.sub.i with very high throughput rates such as 380 million operations per second.

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patent: 3748451 (1973-07-01), Ingwersen
patent: 4152627 (1979-05-01), Priel et al.
patent: 4202039 (1980-05-01), Epenoy et al.
patent: 4287566 (1981-09-01), Culler
patent: 4344151 (1982-08-01), White
patent: 4393468 (1983-07-01), New

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