Information processor performing interrupt operation in two mode

Details Information processor performing interrupt operation in two mode Information processor performing interrupt operation in two mode

1991-04-25

1992-10-27

Chan, Eddie P.

Boots, shoes, and leggings

395375, 395275, 364DIG1, 3642329, 3642421, 3642808, 3642627, 3642473, G06F 946, G06F 930

Patent

active

051596881

ABSTRACT:
An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

REFERENCES:
patent: 3373408 (1968-03-01), Ling
patent: 3909794 (1975-09-01), Soltsien
patent: 4091447 (1978-05-01), Dillon et al.
patent: 4250546 (1981-02-01), Boney et al.
patent: 4530049 (1985-07-01), Zee

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