Semiconductor substrate structure for use in power IC device

Details Semiconductor substrate structure for use in power IC device Semiconductor substrate structure for use in power IC device

1990-09-26

1992-10-27

Hille, Rolf

357 52, 357 20, 357 43, H01L 2704

Patent

active

051594277

ABSTRACT:
A wafer substrate structure has a P type epitaxial wafer layer. An N+ type region separation layer is formed on the wafer layer to define a first closed region and a second region neighboring thereto. Formed in the first region are a P- type layer and an N- type layer stacked thereon and serving as a high-resistance layer for forming the first element. An N- type layer serving as a high-resistance layer exists in the second region of the wafer layer. These high-resistance layers are defined by separating a single semiconductor layer by an N+ type diffused separation layer. Forming a high-voltage transistor as a power element in the first region to be PN junction-separated brings a "double PN junction separation" structure wherein the first region is electrically separated by a PN junction from the second region and the high-voltage transistor is also PN junction-separated in the first region.

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