Timing generator for generating a multiplicty of timing signals

Details Timing generator for generating a multiplicty of timing signals Timing generator for generating a multiplicty of timing signals

1987-06-08

1989-08-08

Heyman, John S.

Excavating

328 75, 371 27, 324 73R, 377 26, 307463, G01R 3128, G06F 1100

Patent

active

048556815

ABSTRACT:
A timing generator for generating a plurality of pulse sequences within a test cycle. Each pulse sequence has a plurality of pulses having a position identified by the data contents of a multiplicity of random access memories. Like numbered lower order bits of each memory are decoded to provide a plurality of pulse sequences corresponding in number to the number of lower order bits. The memories are arranged in a hierarchy. The random access memories are each provided with a separate address counter. The highest order bit of each memory is used to reset the respective memory address counter as well as enable an adjacent higher order memory address counter, and are decoded to define the end of the test cycle.

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