Method and apparatus for reducing area and pin count required in

Details Method and apparatus for reducing area and pin count required in Method and apparatus for reducing area and pin count required in

1996-07-22

1999-07-06

Nguyen, Hoa T.

Excavating

371 671, 365201, G11C 2900

Patent

active

059205733

ABSTRACT:
A reduced silicon area, wide input/output (I/O) comparitor method and apparatus for design-for-test applications includes a plurality of input/output pins (60) and plural arrays of addressable storage cells (32-46). A page mode writing circuit provides, through a common data-in lead (30), plural copies of a test data bit, applied through one of the pins (30), for storage in addressed storage cells (32-46) along a row in each of the arrays of storage cells. A circuit receives an expected data bit (ED), and a readout circuit reads out the stored test data bit from the addressed storage cells along the row in each of the arrays of storage cells. A PRW signal generator (154) responds to a column address change to establish a first potential state on all four quadrant-specific common lines (102, 408, 411, and 413). A plurality of multiplexer circuits (230), each multiplexer circuit associated with two different arrays of storage cells, are arranged to combine the multiple data bits from the associated arrays (32-46) to a reduced number of outputs to the plural comparitors circuits (242, 244, 248, and 250).

REFERENCES:
patent: 4541090 (1985-09-01), Shiragasawa
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4868823 (1989-09-01), White, Jr. et al.
patent: 5075892 (1991-12-01), Choy
patent: 5185744 (1993-02-01), Arimoto et al.
patent: 5301155 (1994-04-01), Wada et al.

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