Frequency-divider circuit with input signal level offset control

Details Frequency-divider circuit with input signal level offset control Frequency-divider circuit with input signal level offset control

1991-11-05

1993-05-25

Sikes, William L.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 48, H03K 2102

Patent

active

052146812

ABSTRACT:
Judgment means provides a first output alternating signal to a .div.2 frequency-divider and also a frequency-division control signal at a first level to operate the .div.2 frequency-divider, when a first input alternating signal is applied to an input terminal. The first output alternating signal frequency divided by the .div.2 frequency divider is applied to an NOR gate, to which a first gate control signal is applied from the judgment means so as to allow the frequency divided first output alternating signal to pass the NOR gate. When a second input alternating signal is applied to the input terminal, the judgment means provides the frequency-division control signal at a second level to the .div.2 frequency-divider which, in turn, provides a second gate control signal to the NOR gate. At this time, the judgment means also provides a second output alternating signal to the NOR gate. The NOR gate with the second gate control signal applied thereto passes the second output alternating signal therethrough. The first and second input alternating signals alternate about different reference levels.

REFERENCES:
patent: 4656649 (1987-04-01), Takahashi
patent: 4820993 (1989-04-01), Cohen et al.
patent: 4845727 (1989-07-01), Murray
patent: 5077764 (1991-12-01), Yamashita
patent: 5084907 (1992-01-01), Maemura

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