Thin film field effect transistor, CMOS inverter, and methods of

Details Thin film field effect transistor, CMOS inverter, and methods of Thin film field effect transistor, CMOS inverter, and methods of

1992-01-28

1993-05-25

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257369, 257377, 437 41, 437 44, 437 57, 437106, 437153, 437186, 437915, 437200, H01L 2701, H01L 21265

Patent

active

052142957

ABSTRACT:
Disclosed herein is a thin film field effect transistor and a method for producing such a thin film transistor. The thin film transistor has a transistor gate and thin film active and channel regions. The transistor gate has a top surface and sidewalls which are coated with a thin gate insulating layer. A thin semiconductor film is provided over the transistor gate and thin gate insulating layer to form a conductively doped thin film channel region and conductively doped thin film active regions. The thin film channel region contacts the thin gate insulating layer opposite the transistor gate top surface and opposite the sidewalls. The transistor gate sidewalls in operation gate the opposite thin film channel region through the thin gate insulating layer. The thin film field effect transistor can be fabricated over an underlying MOSFET to form a CMOS inverter with the transistor gate being common to both the thin film transistor and the MOSFET. In this configuration the thin film channel region contacts the thin gate insulating layer opposite an underlying MOSFET active region. The underlying active region in operation gates the opposite thin film channel region through the thin gate insulating layer.

REFERENCES:
patent: 4814841 (1989-03-01), Masuoka et al.
patent: 4980732 (1990-12-01), Okazawa
A. O. Adan, et al., "Leakage Current In Polysilicon MOS Thin-Film Transistors and an Optimum Self-Aligned Structure for High Density SRAMs," Date Unknown.
M. Ando, et al., "A 0.1 uA Standby Current, Bouncing-Noise-Immune 1 Mb SRAM," IEEE Journ. of Solid State Circuits, pp. 1708-1713, Dec. 1989.
Ikeda et al., "A Polysilicon Transistor Technology For Large Capacity SRAMs," IEDM 1990, pp. 469-472.
H. Chkubo et al., "16 Mbit SRAM Cell Technologies for 2.0 V Operation," NEC Corporation, Date Unknown.

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