Semiconductor test device

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371 21, G01R 3128

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048130435

ABSTRACT:
A semiconductor test device including a function test algorithmic pattern generator which comprises: an ALU unit with shift-in function for conducting a predetermined arithmetical and logical operation against the base data or the output of an ALU output register; the ALU output register being designed to store the output of the ALU and output a function test algorithmic pattern; and a parity detection circuit which conducts a parity detection against an arbitrary group of bits of the ALU output register, and the detection output is input into a shift-in input of the ALU.

REFERENCES:
patent: 4555663 (1985-11-01), Shimizu
patent: 4586181 (1986-04-01), Shimizu
patent: 4670879 (1987-06-01), Okino
patent: 4692920 (1987-09-01), Tannhocuser
patent: 4701919 (1987-10-01), Naitoh
"Self-Testing by Polynomial Division" by Dilip K. Bhavsar and Richard W. Heckelman, General Electric Company, Electronics Laboratory, 1981 IEEE Test Conference, Paper 9.2.

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