Semiconductor device FET with reduced energy level degeneration

Details Semiconductor device FET with reduced energy level degeneration Semiconductor device FET with reduced energy level degeneration

1986-09-16

1989-03-14

James, Andrew J.

357 2312, 357 59, 357 67, H01L 2702

Patent

active

048128899

ABSTRACT:
A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first impurity region of second conductivity which is formed in the substrate, a second impurity region of the second conductivity type which is formed in the substrate and spaced apart from the first semiconductor region, a channel region located between the first and second impurity regions, an insulation layer on the channel region, and a gate electrode on the insulation layer including conductive layer means for decreasing the temperature dependence of the semiconductor device, the layer means including a conductive layer and a semiconductive layer for reducing energy level degeneration.

REFERENCES:
patent: 3738880 (1973-06-01), Laker
patent: 3793090 (1974-02-01), Barile et al.
patent: 4258465 (1981-03-01), Yasui et al.
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4590509 (1986-05-01), Esser et al.
patent: 4612565 (1986-09-01), Shimizu et al.
Murarka, "Refractory Silicides for Integrated Circuits," J. Vac. Sci. Technol., 17(4), Jul./Aug. 1980, pp. 775-792.

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