System and method for high frequency operation of I/O bus

Details System and method for high frequency operation of I/O bus System and method for high frequency operation of I/O bus

1995-12-18

1998-11-17

Shin, Christopher B.

39520063, 395556, 395550, G06F 1342

Patent

active

058389954

ABSTRACT:
An extension to an I/O bus and bridge chip is provided which allows higher speed operations. This includes control logic which switches between different data transfer speeds. A host bridge interconnects a system bus with an I/O bus. Included in the host bridge is both a high frequency and low frequency clock. The bridge chip normally operates at the lower frequency and initiates communication with the I/O at this low frequency. If the I/O device is capable of operating at a higher frequency, then a control signal is transmitted from the I/O device to the bridge chip. In response to the receipt of this signal, control logic in the bridge chip causes the higher frequency clock in the bridge chip to be activated such that the host bridge, bus and I/O device are all then operating at the higher frequency.

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