Multi-stage timer implementation for telecommunications transmis

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 114

Patent

active

058389571

ABSTRACT:
Telecommunications networks require a large number of timers to support the necessary dispatching of tasks. These timers require significant CPU cycles. The present invention describes a method and apparatus for reducing the CPU requirements of timers while maintaining their utility and accuracy by using multi-class periodic timers.

REFERENCES:
patent: 5491815 (1996-02-01), Basso et al.
"Hashed and Hierarchical Timing Wheels: Data Structures for the Efficient Implementation of a Timer Facility" by George Varghese and Tony Lauck, Digital Equipment Corporation, Littleton, MA, ACM 089791-242-X/87/0011/0025, pp. 25-38.
"Timers in OSI Protocols: Specification Versus Implementation" by E. Mumprecht, D. Gantenbein and R. Hauser, Zurich, Switzerland, Aug., 1987, internal IBM publication, pp. 93-98.
APPN High Performance Routing Architecture Reference, Aug., 1995, IBM Document No. SV40-1018-00, IBM Corp., APPN Architecture. Department BUFA, P.O. Box 12195, Research Triangle Park, NC 27709.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multi-stage timer implementation for telecommunications transmis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-stage timer implementation for telecommunications transmis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-stage timer implementation for telecommunications transmis will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-895383

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.