Multi-stage timer implementation for telecommunications transmis

Details Multi-stage timer implementation for telecommunications transmis Multi-stage timer implementation for telecommunications transmis

1996-02-01

1998-11-17

Heckler, Thomas M.

G06F 114

Patent

active

058389571

ABSTRACT:
Telecommunications networks require a large number of timers to support the necessary dispatching of tasks. These timers require significant CPU cycles. The present invention describes a method and apparatus for reducing the CPU requirements of timers while maintaining their utility and accuracy by using multi-class periodic timers.

REFERENCES:
patent: 5491815 (1996-02-01), Basso et al.
"Hashed and Hierarchical Timing Wheels: Data Structures for the Efficient Implementation of a Timer Facility" by George Varghese and Tony Lauck, Digital Equipment Corporation, Littleton, MA, ACM 089791-242-X/87/0011/0025, pp. 25-38.
"Timers in OSI Protocols: Specification Versus Implementation" by E. Mumprecht, D. Gantenbein and R. Hauser, Zurich, Switzerland, Aug., 1987, internal IBM publication, pp. 93-98.
APPN High Performance Routing Architecture Reference, Aug., 1995, IBM Document No. SV40-1018-00, IBM Corp., APPN Architecture. Department BUFA, P.O. Box 12195, Research Triangle Park, NC 27709.

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