Logical, fail-functional, dual central processor units formed fr

Details Logical, fail-functional, dual central processor units formed fr Logical, fail-functional, dual central processor units formed fr

1995-06-07

1998-11-17

An, Meng-Ai T.

3951821, 39520001, G06F 1100

Patent

active

058388940

ABSTRACT:
A computing system includes a pair of central processor units structured to operate in substantial synchronism to each execute the same instruction at substantially the same moment in time of identical instruction streams to achieve a logical central processor unit with fail-functional operation. One of the central processor units includes a pair of processors that execute, instruction by instruction, the instruction stream with checking for fail-fast operation. The other central processor unit includes only a single processor element. The system achieves a low cost fail-functional architecture.

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