Layout system for logic circuit

Details Layout system for logic circuit Layout system for logic circuit

1996-09-30

1998-11-17

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, G06F 1750

Patent

active

058385819

ABSTRACT:
In a layout system of a logic circuit, a buffer inserted into a critical path is arranged/wired in an arranged region of a circuit block of a primitive layout in such a manner that delay time of the critical path in the primitive layout can be limited to an allowable value. The layout system is comprised of unarranged region information extracting means for extracting a position and a size of an unarranged region from layout data after an arranging/wiring process; virtual node inserting means for inserting a virtual node into a wiring segment located adjacent to the unarranged region, the virtual node constituting a connection point between the wiring segment and the unarranged region; wiring parameter extracting means for extracting a wiring parameter constructed of a wiring resistance and a wiring capacitance of the wiring segment; and path delay time calculating means for calculating delay time of a path based upon the wiring parameter and a delay parameter specific to an element.

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